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采用现场可编程门阵列 (FPGA) ,设计了一种用于SDH传输系统中数据通信通道 (DCC)数据帧汇聚与速率适配的电路 .可以将具有不同时钟的 1 2个独立DCC通道中的HDLC数据帧进行提取、缓存并复接成一个时分复用的高速数据链路 ,交给MotorolaMPC860中的多通道通信控制器进行处理 .整个设计采用一片XILINX的xc2s2 0 0pq2 0 8完成 ,使用约 1 7万等效门 ,在HDLC最大帧长为 1kB的情况下 ,允许的多通道通信控制器与DCC通道时钟之间的时钟偏差大于 1 4%,并给出了测试波形
A field-programmable gate array (FPGA) was used to design a circuit for data frame aggregation and rate adaptation of data communication channels (DCC) in an SDH transmission system.It can be used in 12 independent DCC channels with different clocks HDLC data frame to extract, cache and multiplexed into a time-multiplexed high-speed data link to the multi-channel communication controller MotorolaMPC860 for processing the entire design using a XILINX xc2s2 0 0pq2 0 8 to complete the use of about 1 The equivalent of 70,000 gates, with a maximum HDLC frame size of 1kB, the clock skew between the allowed multi-channel communications controller and the DCC channel clock is greater than 14% and the test waveform is given