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为减小功率放大器的尺寸和提高放大器的效率,可以利用晶体管的漏端寄生结电容作为E类射频功率放大器的分流电容。文章提出根据晶体管漏体寄生结电容来设计E类CMOS功率放大器,在BSIM3V3漏体结电容模型的基础上,分析了漏端边缘电容对设计的影响,同时,采用数据拟合来降低计算复杂度。仿真结果表明,该方法可运用于实际设计。文章的研究为低功耗E类CMOS功率放大器的小型化设计提供了一种新的方法,具有一定的应用参考价值。
To reduce the size of the power amplifier and improve the efficiency of the amplifier, the parasitic junction capacitance of the drain of the transistor can be utilized as the shunt capacitance of the RF amplifier of class E. Based on the parasitic junction capacitance of transistors, a class E CMOS power amplifier is proposed. Based on the BSIM3V3 drain-to-node junction capacitance model, the influence of drain-edge capacitance on the design is analyzed. At the same time, data fitting is adopted to reduce the computational complexity . Simulation results show that the method can be applied to the actual design. The research of the article provides a new method for the miniaturization design of low-power class-E CMOS power amplifier, which has certain application reference value.