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设计并实现了一种基于FPGA的二进制连续相位调制(CMP)解调器。该解调器针对二进制部分响应调制方式,采用Viterbi译码方法进行解码。文中针对路径度量值随着译码序列增长可能发生溢出的现象,提出了一种新的防止路径度量值溢出方法。最后使用VHDL硬件描述语言将该解调器的设计进行实现,运用Modelsim仿真软件进行了功能仿真,并将仿真结果与MATLAB数据比较分析。该解调器的FPGA设计能够得到正确的解码结果,最终证明了该方法的有效性。
An FPGA-based binary continuous phase modulator (CMP) demodulator was designed and implemented. The demodulator for the binary part of the response modulation, using Viterbi decoding method for decoding. Aiming at the phenomenon that the path metric value may overflow along with the increase of the decoding sequence, a new method to prevent path metric overflow is proposed. At last, the design of the demodulator is realized by using VHDL hardware description language, and the functional simulation is carried out by using Modelsim simulation software. The simulation results are compared with the MATLAB data. The demodulator FPGA design can get the correct decoding results, and finally prove the effectiveness of the method.