时序设计是数字系统性能的关键 ,在高层设计方法中对时序的控制进一步抽象 ,我们在介绍电路时钟和时序的基础上分析了 RTL 电路的时序模型 ,该模型讨论了 RTL 电路的时延路径、建立保持时间以及系统正常工作的条件 ,并据此提出了相应的设计策略 ,通过实践证明这种设计方法是行之有效的 Timing design is the key to the performance of digital system. The timing control is further abstracted in the high-level design method. Based on the introduction of the circuit clock and timing, we analyze the timing model of RTL circuit. The model discusses the delay path of RTL circuit, Establish the maintenance time and the conditions of the normal work of the system, and accordingly put forward the corresponding design strategy, proved by practice that this design method is effective