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随着集成电路特征尺寸进入纳米尺度,摩尔定律的延续受到一定的挑战,纳米技术代的晶体管亟需全新的材料、器件结构和工艺集成技术。在器件结构方面,无结型场效应晶体管由于其近似理想的电流电压特性、优良的等比例缩小能力以及极其简单的制造工艺,受到了人们广泛的关注。通过三维数值仿真工具Synopsys Sentaurus 3DTCAD,对多栅的无结型MOS晶体管进行了数值模拟仿真。并在此基础上探究了无结型器件沟道形状对其电学特性的影响,提出了具有倒角正梯形沟道的多栅无结型晶体管结构,验证了其相较于普通无结多栅型器件更加优良的电学特性,以及栅长下降至20nm以下节点时对短沟道效应的进一步抑制作用。
As integrated circuit feature sizes enter the nanometer scale, the continuation of Moore’s Law is challenged, and nanotechnology-based transistors are in urgent need of new materials, device structures, and process integration technologies. In terms of device structure, junctionless field-effect transistor (FET) has drawn much attention due to its approximate ideal current-voltage characteristics, excellent scaling performance, and extremely simple manufacturing process. The numerical simulation of multi-gate junctionless MOS transistors is performed by using Synopsys Sentaurus 3DTCAD, a three-dimensional numerical simulation tool. Based on this, the influence of the channel shape of the junctionless device on its electrical characteristics was investigated. A multi-gate junctionless transistor structure with chamfered regular trapezoidal channel was proposed. Compared with the common non-junction multi-gate Type device more excellent electrical characteristics, as well as the gate length down to 20nm below the node on the short-channel effect further inhibited.