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目前,面向网络流实时处理的正则表达式匹配技术面临两方面的挑战:一方面,复杂或大规模规则集会导致DFA存储空间爆炸的问题;另一方面,传统计算机的串行DFA匹配技术很难满足对高速主干网的线速深度包检测。本文提出了一个基于改进游程编码的DFA压缩算法,并在FPGA上高效实现了该压缩DFA的匹配引擎。测试结果表明规则集的单个DFA的吞吐率均大于800Mbps,在FPGA块内存最大利用率情况下的理论最大吞吐率达到49.5Gbps。
At present, the regular expression matching technology for network stream real-time processing faces two challenges: on the one hand, complex or large-scale rule sets cause the explosion of DFA storage space; on the other hand, the traditional computer serial DFA matching technology is difficult Meet the wire-speed deep packet inspection of high-speed backbone network. In this paper, a DFA compression algorithm based on improved run-length coding is proposed, and the matching engine of the compressed DFA is efficiently implemented on the FPGA. The test results show that the throughput of a single DFA in the rule set is greater than 800Mbps, and the theoretical maximum throughput rate reaches 49.5Gbps under the maximum utilization of FPGA block memory.