提出了一种实现整数转浮点数的新的设计方法 ,并且对方法的正确性给予了证明 .采用这种设计方法 ,实现了求补和舍入的合并并行 ,使关键路径的延时比常规的电路设计方案减少了 15级门 ,同时降低了电路规模 .关键路径延时的减小 ,使这一转换可以在单周期内完成 .另外 ,该方法实现了位长自适应 ,只需花费很少的电路规模和延时实现控制 ,就可以适应长整型、整型到单、双精度浮点数的转换 ,增强了电路功能 .这一设计方法同样适用于其逆转换 .该转换模块采用 Fujitsu CE71库设计 ,在 10 0 MHz主频下经仿真验证 ,结果正确 ,已经应用到实际工程中 . Proposed a new design method to achieve the integer floating-point number, and proved the correctness of the method.Using this design method, the parallelization of the complement and rounding is realized, and the delay of the critical path is longer than the conventional Of the circuit design program to reduce the door 15, while reducing the circuit size.Decreasing the critical path delay, so that this conversion can be completed in a single cycle.In addition, the method to achieve a bit-length adaptive, it takes only a very Less circuit size and delay to achieve control, you can adapt to the long integer, integer to single, double precision floating-point conversion, enhanced circuit functions.This design method also applies to its inverse conversion.The conversion module uses Fujitsu CE71 library design, simulation at 10 0 MHz frequency verified, the results are correct, has been applied to the actual project.