A p-type low-temperature poly-Si thin film transistors(LTPS TFTs) integrated gate driver using 2 nonoverlapped clocks is proposed.This gate driver features charge-sharing structure to turn off buffer TFT and suppresses voltage feed-through effects.It is analyzed that the conventional gate driver suffers from waveform distortions due to voltage uncertainty of internal nodes for the initial period.The proposed charge-sharing structure also helps to suppress the unexpected pulses during the initialization phases.The proposed gate driver shows a simple circuit,as only 6 TFTs and 1 capacitor are used for single-stage,and the buffer TFT is used for both pulling-down and pulling-up of output electrode.Feasibility of the proposed gate driver is proven through detailed analyses.Investigations show that voltage bootrapping can be maintained once the bootrapping capacitance is larger than0.8 pF,and pulse of gate driver outputs can be reduced to 5μs.The proposed gate driver can still function properly with positive V_(TH)shift within 0.4 V and negative V_(TH) shift within-1.2 V and it is robust and promising for high-resolution display. A p-type low-temperature poly-Si thin film transistors (LTPS TFTs) integrated gate driver using 2 nonoverlapped clocks is proposed. This gate driver features charge-sharing structure to turn off the buffer TFT and suppresses voltage feed-through effects. It is is analyzed that the conventional gate driver suffers from waveform distortions due to voltage uncertainty of internal nodes for the initial period.The proposed charge-sharing structure also helps suppress the unexpected pulses during the initialization phases. proposed proposed gate driver shows a simple circuit, as only 6 TFTs and 1 capacitor are used for single-stage, and the buffer TFT is used for both pulling-down and pulling-up of output electrode. Feasibility of the proposed gate driver is proven through detailed analyzes. Investigations show that voltage bootrapping can be maintained once the bootrapping capacitance is larger than 0.8 pF, and pulse of gate driver outputs can be reduced to 5μs.The proposed gate driver can still function pro perly with positive V_ (TH) shift within 0.4 V and negative V_ (TH) shift within-1.2 V and it is robust and promising for high-resolution display.