论文部分内容阅读
本文对维持阻塞触发器的设计要点进行了归纳,发现在目前的传统设计中有二条连接线是可以节省的,实验也已予证实。 图1表示了一个由六个与非门组成的D型维持阻塞触发器,它的设计要点是 1.具有存贮信号的能力,具有互补的双轨输出。 2.受时钟脉冲cp的控制,只有当时钟来到时存贮的状态信号才发生变化。新状态Q′由激励输入D来决定:Q′=D。 3.在时钟cp来到时只发生一次Q→Q′的状态转换,以避免在工作中“空翻”的发生。
This article summarizes the design considerations for maintaining a blocking flip-flop and finds that there are two connections in the current traditional design that can be saved and experimented with. Figure 1 shows a D-type maintenance blocking flip-flop consisting of six NAND gates. It is designed with the ability to store signals with complementary dual rail outputs. 2. By the clock pulse cp control, only when the clock comes when the storage state signal changes. The new state Q ’is determined by the stimulus input D: Q’ = D. 3. Only a Q → Q ’state transition occurs when clock cp arrives to avoid “rollover” in the job.