提出了一种针对标准单元库中单元逻辑功能进行自动仿真验证的方法,验证了55nm标准单元库中单元逻辑功能的正确性。该方法能自动提取设计文档中的单元逻辑,根据提取结果中输入端的数量自动生成测试向量,并以此测试向量生成参考逻辑值,整个过程只需0.708μs。采用仿真工具对标准单元库文件进行仿真,将得到的仿真值自动与参考值对比,验证了库单元逻辑的正确性,提高了标准单元库功能验证的效率。 A method of automatic simulation verification of unit logic function in standard cell library is proposed, which verifies the correctness of cell logic function in 55nm standard cell library. This method can automatically extract the unit logic in the design document, automatically generate test vectors according to the number of input terminals in the extraction result, and use this test vector to generate reference logic values. The whole process only needs 0.708μs. The simulation software is used to simulate the standard cell library file, the simulation value is automatically compared with the reference value to verify the correctness of the library cell logic and improve the efficiency of standard cell library function verification.