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针对数字通信系统中接收端同步时钟的获取问题,本文以M序列为传输序列,通过对伪随机序列性质的分析,给出具体的位同步时钟提取和恢复算法。同步时钟提取算法的关键在于原始序列的恢复和最大游程的确定。通过设计模拟电路恢复原始序列,在FPGA或DSP上设计算法确定最大游程恢复出同步时钟。由于恢复的实时时钟往往有时延抖动,最后还需要通过单片机对数据进行拟合来获得一个准确的时钟。
Aiming at the problem of receiver clock synchronization in digital communication system, this paper takes M sequence as transmission sequence and gives the concrete algorithm of bit synchronization clock extraction and recovery by analyzing the nature of pseudo-random sequence. The key to synchronous clock extraction algorithm lies in the recovery of the original sequence and the determination of the maximum run length. By designing the analog circuit to recover the original sequence, an algorithm is designed on the FPGA or DSP to determine the maximum run and recover the synchronous clock. Since the recovered real-time clocks tend to have time-delay jitter, they eventually need to fit the data through the microcontroller to get an accurate clock.