Adaptive digital calibration techniques for narrow band low-IF receivers with on-chip PLL

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Digital calibration and control techniques for narrow band integrated low-IF receivers with on-chip frequency synthesizer are presented.The calibration and control system,which is adopted to ensure an achievable signal-to-noise ratio and bit error rate,consists of a digitally controlled,high resolution dB-linear automatic gain control(AGC),an inphase(I) and quadrature(Q) gain and phase mismatch calibration,and an automatic frequency calibration(AFC) of a wideband voltage-controlled oscillator in a PLL based frequency synthesizer.The calibration system has a low design complexity with little power and small die area.Simulation results show that the calibration system can enlarge the dynamic range to 72 dB and minimize the phase and amplitude imbalance between I and Q to 0.08° and 0.024 dB,respectively,which means the image rejection ratio is better than 60 dB.In addition,the calibration time of the AFC is 1.12 μs only with a reference clock of 100 MHz. Digital calibration and control techniques for narrow band integrated low-IF receivers with on-chip frequency synthesizer are presented. The calibration and control system, which is adopted to ensure an achievable signal-to-noise ratio and bit error rate, consists of a digitally controlled, high resolution dB-linear automatic gain control (AGC), an inphase (I) and quadrature (Q) gain and phase mismatch calibration, and an automatic frequency calibration (AFC) of a wideband voltage-controlled oscillator in a PLL based frequency synthesizer.The calibration system has a low design complexity with little power and small die area.Simulation results show that the calibration system can enlarge the dynamic range to 72 dB and minimize the phase and amplitude imbalance between I and Q to 0.08 ° and 0.024 dB , respectively, which means the image rejection ratio is better than 60 dB. In addition, the calibration time of the AFC is 1.12 μs only with a reference clock of 100 MHz.
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