基于wormhole交换策略和目的地址确定性路由算法,采用三级流水线的结构实现了片上网络中的路由节点.该路由节点适用于Mesh和Torus拓扑,并采用虚通道技术增加吞吐量.在Xilinx的FPGA上实现后可知,该路由节点最高可工作在130 MHz的时钟频率上,传输带宽为20.8Gb/s. Based on the wormhole exchange strategy and destination address deterministic routing algorithm, a routing node in the on-chip network is realized by a three-stage pipeline architecture, which is suitable for Mesh and Torus topologies and uses virtual channel technology to increase the throughput. In Xilinx FPGA Upon implementation, it can be known that the routing node can work at a maximum clock frequency of 130 MHz and the transmission bandwidth is 20.8 Gb / s.