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本文阐述了使用CPLD实现PCI总线数据采集卡的接口设计方法 ,并且介绍了一种用VHDL语言进行PCI总线目标模块设计的方案 ,详细介绍了配置空间的设置和时序状态机的设计方法。
This article describes the design method of the interface of PCI bus data acquisition card using CPLD and introduces a scheme of designing the target module of PCI bus in VHDL language. The configuration of the configuration space and the design method of timing state machine are introduced in detail.