本文提出一个新的宏单元模式分级布图规划方法.布图规划分三个阶段进行:芯片物理分级构造、布图规划和布图规划修正.主要特点包括:松弛对布图拓扑结构的约束、模块“自然”结群构造设计物理分级、采用解析方法求解面积规划问题、基于一个新的Steiner树算法求布线规划、包含模块面积估计和布线面积估计.实验结果表明提出的方法可以在满足不同形状和I/O设计目标的同时得到很高的芯片面积利用率. In this paper, a new macro-cell hierarchical layout planning method is proposed.The layout planning is divided into three stages: chip physical hierarchy construction, layout planning and layout planning revision.The main features include: Relaxation constraints on the layout topology, module The “natural” knot cluster structure design is physically graded, and the analytic method is used to solve the area planning problem. Based on a new Steiner tree algorithm, the routing planning including module area estimation and layout area estimation is presented. The experimental results show that the proposed method can meet the needs of different shapes, I / O design goals at the same time get a high chip area utilization.