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研究了CMOS模拟集成电路的不同版图结构对电路性能的影响规律,探讨了不同版图结构对工艺波动的抑制作用。通过采用90 nm CMOS工艺设计了8种不同宽长比(W/L)的数模转换器(DAC),分别利用单栅与多指栅结构实现该DAC电流源输出驱动管阵列,并将其作为研究对象进行了分析。通过分析金属氧化物半导体场效应晶体管(MOSFET)阈值电压VTH和DAC输出电压Vout的实测数据,对CMOS模拟集成电路的最优版图设计方案进行了探讨。最后,利用本研究结果设计了一款90 nm工艺的低功耗CMOS运算放大器,相比传统版图结构,该放大器的工艺波动抑制能力提高了5.87%。
The influences of different layout structures of CMOS analog integrated circuits on circuit performance are studied, and the inhibition of process fluctuation by different layout structures is discussed. By using 90 nm CMOS technology, eight kinds of DACs with different W / L ratios are designed. The array of DAC driver current sources is driven by single-gate and multi-gate respectively. As the research object was analyzed. By analyzing the measured data of MOSFET threshold voltage VTH and DAC output voltage Vout, the optimal layout design of CMOS analog integrated circuit is discussed. Finally, a low-power CMOS op-amp with a 90-nm process was designed using the results of this study. Compared with the conventional layout, the amplifier’s process ripple rejection is improved by 5.87%.