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介绍了采用蒙哥马利模乘法算法和指数的从右到左的二进制方法,并根据大整数模乘法运算和VLSI实现的要求进行改进的RSA处理器,在提供高速RSA处理能力的同时,可抵抗某些定时分析攻击和功耗分析攻击。该RSA处理器在其模乘法器中使用了CSA(进位保留加法器)结构以避免长进位链,并采用一种新型(4∶2)压缩器结构以减少面积和延迟。提出了信号多重备份的方法,解决信号广播带来的大的负载和线长问题。数据通路的设计采用一种基于多选器的动态重构方法,其模乘法器可以执行一个1024位的模乘幂运算,也可以并行执行2个512位的模乘幂运算,从而支持基于中国剩余定理的加速策略。
An RSA processor that uses a Montgomery modulus multiplication algorithm and exponent right-to-left binary method and improves upon the requirements of large integer modular multiplications and VLSI implementations is presented that provides high-speed RSA processing while being resistant to certain Timing Analysis Attack and Power Analysis Attacks. The RSA processor uses a CSA (Carry Reserved Adder) structure in its modular multiplier to avoid long carry chains and uses a new (4: 2) compressor structure to reduce area and latency. A method of multiple signal backup is proposed to solve the problem of large load and line length caused by signal broadcasting. Data path design uses a multi-selector dynamic reconstruction method, the modular multiplier can perform a 1024-bit modular exponentiation, you can also parallel execution of two 512-bit modular exponentiation, which supports based on China Remaining Theorem Acceleration Strategy.