FPGA application independent test is very time-consuming due to repetitively loading of test configuration bitstreams into the FPGA and applying test stimuli.Statistics shows that over 95%of FPGA application independent test time is spent on loading the test configuration bitstreams.Therefore,reducing the number of loading times could significantly reduce the FPGA test time.In this paper,a new approach which can significantly reduce the FPGA test time will be presented.In this new approach,a configuration SRAM routing strategy is used first to enhance the correlation of the test bitstream configurations,then,on-chip test configuration generation structures are designed to transform a test bitstream configuration into other ones within limited cycles.Experimental results show that the proposed technique can at least reduce the configuration loading time by 81%,while getting 100%test coverage.The hardware overhead is less than 1.2%upon the whole chip without any performance penalty.