惠普实验室制造了一台带有22万个已经为人所知错误的实验计算机。对于那些熟知惠普产品卓越品质的人们来说,这是一条令人震惊的消息。人们会问:“那么,其他什么是新的呢?”新的地方在于这台计算机可以产生正确的结果,并且比传统的单处理器的高端工程工作站快100倍。这台实验计算机是巨大的并行Teramac,“Tera”表示目标速度是每秒万亿次运算,“mac”代表多元体系计算机。建立这样的一个系统,它保存过去的提高计算机性能的趋势,并且可以不必需要花费300亿美元来制造复杂的、无错的,由传统设计的系统,而且很有可能到2012年还在使用。Teramac正是为了达到这个目的而做的最开始的步骤。 Teramac包含有864个完全相同的定制FPGA(Field Programmable Gate Arravs,现场可编程门阵列)芯片。在调查预算中发现,这样的复杂设计会很昂贵。其他的是有缺陷的传统的双芯片模块。这项计划决定制造一个容错的机器,它应用7％的FPGA,4％的连接,7％的电路板就可以完成功能。在系统中,其他部分的错误可以被检测到,并有软件把它们隔离开。定位错误的时间由机器大小的比例决定,这意味着,这种方法在大 HP Labs created a test computer with 220,000 already known errors. This is a shocking news for those of you who know the great qualities of HP products. People would ask, “So, what’s new?” What’s new is that this computer produces the right results and is 100 times faster than a traditional single-processor, high-end engineering workstation. The experimental computer is a huge parallel Teramac, “Tera” said the target speed is trillion operations per second, “mac” on behalf of multi-system computer. Building such a system that preserves the past trend of increasing computer performance without the need to spend $ 30 billion to build complex, error-free, conventionally designed systems and is likely to be in use by 2012. Teramac is the very first step in this direction. Teramac includes 864 identical FPGA (Field Programmable Gate Arravs, Field Programmable Gate Array) chips. In the survey budget, such complex designs can be expensive. Others are defective traditional two-chip modules. The plan decided to create a fault-tolerant machine that would function with a 7% FPGA, a 4% connection, and a 7% board. In the system, other parts of the error can be detected, and software to isolate them. The time to locate the error depends on the size of the machine, which means that this method is large