提出了一种优化时延的增量式布局算法 ,该算法根据时延分析的结果在迭代求解的过程中动态调整线网权值 .在此基础上 ,提出了三种同时优化时延和拥挤度的多目标优化的布局算法 ,在满足时延和拥挤度约束的前提下对关键路径上的单元进行位置调整 .实验结果表明该算法能够有效地提高芯片速度并降低走线拥挤 .对于优化线长得到的布局方案 ,最长路径上的时延值在增量式布局之后能够降低 10 % . This paper proposes an incremental layout algorithm with optimized delay, which dynamically adjusts the weights of the network during the iterative process based on the results of the delay analysis, and on the basis of which three simultaneous optimization delays and crowding Degree of the multi-objective optimization layout algorithm, to meet the delay and congestion constraints on the premise of the unit on the key path position adjustment.The experimental results show that the algorithm can effectively improve the chip speed and reduce the line congestion.For the optimization of the line The resulting layout scheme, the longest path delay value in incremental layout can be reduced by 10%.